Research output per year
Research output per year
Fingerprint
Dive into the research topics where Algorithms and Logics for Verification is active. These topic labels come from the works of this organisation's members. Together they form a unique fingerprint.
Profiles
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Tim A.C. Willemse
- Mathematics and Computer Science, Formal System Analysis - Associate Professor
- Mathematics and Computer Science, Algorithms and Logics for Verification - Associate Professor
Person: UHD : Associate Professor
Research output
- 1 Article
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Correct and efficient antichain algorithms for refinement checking
Laveaux, M., Groote, J. F. & Willemse, T. A. C., 2021, In: Logical Methods in Computer Science. 17, 1, p. 8:1-8:40 40 p., 8.Research output: Contribution to journal › Article › Academic › peer-review
Open Access
Student theses
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An approachable language for formal requirements
Author: Nogarede, K., 11 Dec 2019Supervisor: Willemse, T. A. (Supervisor 1), Schiffelers, R. R. (External coach) & Groote, J. F. (Supervisor 2)
Student thesis: Master
File -
Code generation and model-based testing in context of OIL
Author: Frenken, M., 10 Dec 2019Supervisor: Willemse, T. A. (Supervisor 1) & van Gool, L. C. (External coach)
Student thesis: Master
File