Project Details
Description
Optical fibers transport the majority of the IP traffic around the world. Over the last years, we have seen an explosive increase of data rates in fibre optics. For instance, in the short-haul domain, the traffic between data centers experienced a 400% growth from 2016 to 2021. This growth is a challenge not only to the technology demands but also to energy consumption. A single state-of-the-art optical transponder can reach a total power consumption of 700W (≈291pJ/bit). Applying Soft-Decision Forward Error Correction (SD-FEC) decoders would be superior in such multi-gigabit per second systems, but their power consumption is up to two orders of magnitude higher (hundreds of pJ/bit) than Hard-Decision Forward Error Correction (HD-FEC) decoders. However, choosing the technology with better energy efficiency comes with a cost: HD-FEC decoders entail a significant performance loss, which will prevent the use of HD-FEC decoders in ultra high-speed fiber optics. More broadly, such drawbacks will also make HD-FEC decoders impractical for beyond 5G mobile communications and future wireless local area network (WiFi-like) standards. In order not to increase future high-speed communication systems’ power consumption further, the error correction algorithms needs to be replaced with completely new approaches.
Recently, we made an innovation in tackling the challenge above, by combining high-performance SD-FEC and low-power HD-FEC in a hybrid FEC system (HY-FEC, see Fig. 1). The core structure of our proposed HY-FEC is similar to standard HD-FEC (see Fig. 2), and soft values are only used to improve the overall performance, making HY- FEC hardware friendly from an algorithmic level perspective. In particular, we have demonstrated that our approach is able to close the performance gap between SD-FEC and HD-FEC, but with at least one order of magnitude lower energy consumption than that of SD-FEC.
Furthermore, we have recently also discovered that with approximately-realised constellation shaping (SH) techniques applied to high-order constellations, higher data rates than that of systems without shaping can be attained with low-complexity (LC). In addition, we showed that LC-SH can be optimised for high-speed optical communications and devised an intellectual-property (IP)-protected algorithm for this purpose. We believe that the combination of LC-SH and HY-FEC with modest power consumption is the best solution for future high-speed communication systems. This combination forms the core of this project (see Fig. 1).
This project aims at establishing technical feasibility of our IP-protected algorithmic approaches which we previously introduced. The feasibility will be based on hardware implementations and thorough testing. Our ultimate goal is to obtain performance levels using SHY-FEC similar to those using traditional SD-FEC architectures without shaping, but with at least one order of magnitude lower energy consumption.
Recently, we made an innovation in tackling the challenge above, by combining high-performance SD-FEC and low-power HD-FEC in a hybrid FEC system (HY-FEC, see Fig. 1). The core structure of our proposed HY-FEC is similar to standard HD-FEC (see Fig. 2), and soft values are only used to improve the overall performance, making HY- FEC hardware friendly from an algorithmic level perspective. In particular, we have demonstrated that our approach is able to close the performance gap between SD-FEC and HD-FEC, but with at least one order of magnitude lower energy consumption than that of SD-FEC.
Furthermore, we have recently also discovered that with approximately-realised constellation shaping (SH) techniques applied to high-order constellations, higher data rates than that of systems without shaping can be attained with low-complexity (LC). In addition, we showed that LC-SH can be optimised for high-speed optical communications and devised an intellectual-property (IP)-protected algorithm for this purpose. We believe that the combination of LC-SH and HY-FEC with modest power consumption is the best solution for future high-speed communication systems. This combination forms the core of this project (see Fig. 1).
This project aims at establishing technical feasibility of our IP-protected algorithmic approaches which we previously introduced. The feasibility will be based on hardware implementations and thorough testing. Our ultimate goal is to obtain performance levels using SHY-FEC similar to those using traditional SD-FEC architectures without shaping, but with at least one order of magnitude lower energy consumption.
Layman's description
This project studies the technical feasibility of our previously-introduced hybrid decoding and low-complexity shaping algorithms based on hardware implementations.
| Status | Active |
|---|---|
| Effective start/end date | 1/01/21 → 30/06/22 |